1. Field of the Invention
The present invention relates generally to software design. The invention is more particularly related to estimation of execution time of software. The invention is still more particularly related to the estimation of execution times of microprocessor based (embedded) software.
2. Discussion of Background
Embedded system designers are continually under increased pressure to reduce the design turnaround time of software and electronics, and often, at the same time, facing continuously changing specifications. One of the major design validation problems is the evaluation of different HW/SW partitions.
Today's approaches are often carried out at the co-verification level—a virtual prototype of the system under validation is built. For example, FIG. 1 provides an example architecture for Hardware/Software Co-Verification From Post-Partitioning Through Physical Prototype. The architecture supports hardware simulation and software development tools.
In today's approaches, the embedded SW is compiled and run on a Instruction Set Simulator (ISS) while the hardware part is simulated by running actual VHDL or Verilog implementations on a logic simulator—the communication between the two partitions being simulated at the bus transaction level. The clear advantage of this approach resides in the accuracy of the simulation results. The disadvantage is in the simulation speed—complete system simulations can be too slow for exploring the design space efficiently. Therefore, in order to reduce the turnaround time, the level of abstraction is raised.
Separating behavior from architecture is a key paradigm for achieving such a goal. In this way behavior and the architecture can co-evolve: while architecture requirements (e.g. cost) may lead to behavior modifications, new constraints in the behavior may require architectural changes. Good system design practice maintains an abstract specification while allowing independent mapping of behavior onto architecture. This is the essence of what has been termed function/architecture co-design and that provides the basis for VCC methodology.
VCC is a design tool developed by Cadence Design Systems for Virtual Component Co-Design. The VCC environment supports both Intellectual Property and Virtual Component based design flow where the architectural IPs are represented in terms of their performance models and are used to back-annotate the behavioral description of the design with timing information. To make sure that the HW-SW trade-offs are accurately explored it is key to provide accurate estimates of execution time of the behaviors that are mapped to SW implementations.
The VCC SW estimation framework models both the target system (CPU instruction set, target compiler, etc.) and the structure of the software program at an abstraction level that makes the estimation time reasonable without losing too much accuracy. However, as noted above, designers are still facing increased pressure to reduce design time, and, increased accuracy is also helpful in turnaround and product quality.